1. Field of the Invention
The present invention relates to a level shifter capable of improving the safety of a high-side driver.
2. Description of Related Art
FIG. 1 is a circuit diagram illustrating a level shifter according to a related art. This level shifter includes resistors R1 to R7, a pulse generator 10, transistors MN1 to MN4, a flip-flop FF1, a buffer BF1, and inverters INV4 and INV5.
The resistor R1 has a first end connected to a power source of the level shifter and a second end connected to a drain of the transistor MN3. The transistor MN3 has the drain connected to the second end of the resistor R1, a source connected through the resistor R3 to the ground, and a gate connected to the pulse generator 10. Between the drain of the transistor MN3 and the ground, there is parasitic capacitance C1. The resistor R2 has the same resistance value as the resistor R1 and includes a first end connected to the power source of the level shifter and a second end connected to a drain of the transistor MN4.
The transistor MN4 has the drain connected to the second end of the resistor R2, a source connected through the resistor R4 to the ground, and a gate connected to the pulse generator 10. Between the drain of the transistor MN4 and the ground, there is parasitic capacitance C2.
According to an input signal, the pulse generator 10 turns on/off the transistors MN3 and MN4. As illustrated in FIG. 1 under the pulse generator 10, the pulse generator 10 provides the gate of the transistor MN3 with a set pulse signal in response to a rise of the input signal and the gate of the transistor MN4 with a reset pulse signal in response to a fall of the input signal.
The resistors R5 and R6 and transistors MN1 and MN2 faun. a control part. The control part generates a set signal if the transistor MN3 is ON, a reset signal if the transistor MN4 is ON, and no signal if there is no voltage difference between the drain of the transistor MN3 and the drain of the transistor MN4.
The resistor R5 has a first end connected to the power source of the level shifter and a second end connected to a drain of the transistor MN1. The transistor MN1 has the drain connected to the second end of the resistor R5, a source connected to the drain of the transistor MN3, and a gate connected to the drain of the transistor MN4. The drain of the transistor MN1 is also connected through the inverter INV4 to a set terminal S of the flip-flop FF1.
The resistor R6 has the same resistance value as the resistor R5 and includes a first end connected to the power source of the level shifter and a second end connected to a drain of the transistor MN2. The transistor MN2 has the drain connected to the second end of the resistor R6, a source connected to the drain of the transistor MN4, and a gate connected to the drain of the transistor MN3. The drain of the transistor MN2 is also connected through the inverter INV5 to a reset terminal R of the flip-flop FF1.
The resistors R5 and R6 are pull-up resistors for the transistors MN1 and MN2, respectively. There is a relationship of R1<<R5. The resistor R1 primarily converts a low-side driving current into a voltage whose amplitude is dependent on the resistance value of the resistor R1. The transistors MN1 and MN2 form a common mode rejection circuit, so that a voltage difference between a voltage across the resistor R1 and a voltage drop by the transistor MN1 is equal to a voltage across the resistor R5 that is to be detected. The same is applicable to the resistor R2 side.
Potential of the power source of the level shifter is potential at a positive electrode of a power source E2 and reference potential of the level shifter is potential at a negative electrode of the power source E2. The power source E2 is connected in parallel with a capacitor C1. The negative electrode of the power source E2, i.e., the reference potential of the level shifter is connected to a connection point between a source of a switching element Q1 and a load L. A threshold of each of the detective inverters INV4 and INV5 connected to the resistors R5 and R6, respectively, is properly set in the range of 20% to 80% of a voltage difference between the power source potential and the reference potential.
According to a set or reset signal generated by the control part, the flip-flop FF1 provides a level-shifted output signal OUT, which is a level-shifted signal of an input signal. The output signal OUT from the flip-flop FF1 is applied through the buffer BF1 and resistor R7 to a gate of the high-side switching element Q1. A drain of the switching element Q1 is connected to a DC power source El and the source thereof is connected through the load L to the ground.
Operation of the level shifter of FIG. 1 will be explained with reference to the timing chart of FIG. 2 . The operation explained below is when a set pulse is supplied to the level shifter. Operation when a reset pulse is supplied to the level shifter is similar to this.
At time t20, the pulse generator 10 applies the set pulse to the gate of the transistor MN3, to turn on the transistor MN3 and pass a current to the resistor R1. This results in creating a voltage difference between the first and second ends of the resistor R1 and decreasing a source voltage of the transistor MN1. When the gate-source voltage of the transistor MN1 exceeds a threshold voltage thereof, the transistor MN1 turns on to pass a current to the resistor R5. When a voltage drop across the resistor R5 reaches the threshold of the inverter INV4, the inverter INV4 outputs a set signal to the flip-flop FF1. The flip-flop FF1 outputs a high-level signal to the gate of the high-side switching element Q1, thereby turning on the switching element Q1.
Operation of the level shifter of FIG. 1 in an abnormal situation will be explained with reference to the timing chart of FIG. 3. The abnormal situation or a malfunction may occur when the load L is a motor, a transformer, or the like whose circuit pattern involves an inductance component, and if occurs, it may drop the reference potential of the level shifter to negative.
The abnormal situation may also occur when the pulse width of an input signal to the pulse generator 10 is too narrow during, for example, a soft start period or standby period. If the input pulse width is too narrow, the level-shifted output signal OUT from the level shifter will be too thin to properly turn on the switching element Q1 or sustain the reference potential of the level shifter.
In FIG. 3, the reference potential of the level shifter decreases to negative without increasing. Even in a normal state, it is necessary to take into consideration that the reference potential of the level shifter may become negative at the ON/OFF timing of the switching element Q1 due to the reactance components of the load L and circuit patterns. Namely, it is necessary to assume that, during a period in which the reference potential of the level shifter is negative, a set or reset signal is sent from the low side to the high side. It is also necessary to consider that, even when the reference potential is positive, the power source potential may decrease its potential.
If the reference potential of the level shifter becomes 0 [V] or lower, the absolute voltage value of the power source of the level shifter decreases. In this situation, a consideration is made on the series circuit including the resistor R1, transistor MN3, and resistor R3 to transfer a set signal from the low side to the high side. When the transistor MN3 turns on in response to a set signal from the pulse generator 10, a voltage dividing ratio of the series-connected resistors R1 and R3 determines a voltage across the resistor R1. The voltage across the resistor R1 is detected by the control part and inverter INV4 and the set signal is transferred to the high-side switching element Q1.
This related art is disclosed in Japanese Unexamined Patent Application Publication No. 2011-109843.